Printed circuit boards mounting semiconductor elements are fabricated with numerous capacitors on the periphery of each LSI (Large Scale Integration) chip to prevent noise. When a rapid load i is imparted to an LSI chip due to a clock operation, a voltage drop ΔV occurs owing to resistance R and inductance L, which exist in lines between the power source and the LSI chip, in accordance with Equation (1) as follows.ΔV=R×i−L×di/dt  (1)
The reason why the sign of L is minus (−) is that an induced electromotive force occurs to cancel out a current instantly occurred. Therefore, the voltage drop ΔV increases as R and L of lines and a load fluctuation di increase, or as a varying time dt decreases. Recently, LSI chips have advanced so that they can operate at high-speed clock frequencies, which exceed several hundreds Mega-hertz. That is, the voltage drop ΔV increases when a rise time tr decreases as the clock frequency increases since the rise time tr of a pulse waveform in a digital circuit is equivalent to the load varying time dt.
As a measure to reduce the voltage drop ΔV, it is an effective measure to juxtapose capacitors between the power line and the ground line of an LSI chip. These capacitors are generally called decoupling capacitors. Since an increased clock frequency of an LSI chip makes it difficult to timely compensate for a temporary voltage drop due to load fluctuation by way of the power source, decoupling capacitors, juxtaposed with an LSI chip, are used to supply electric charge so as to compensate for a voltage drop of the LSI chip. However, ΔV according to Equation (1) has still occurred under influences of equivalent series resistance (ESR) and equivalent series inductance (ESL) of capacitors, wiring resistance R and wiring inductance L between each capacitor and each LSI chip.
Recently, high clock frequencies increased in the GHz order leads to a problem in that inductance L of wiring between decoupling capacitors and an LSI chip cannot be ignored. To solve this problem, some documents (e.g. Patent Documents 1 to 6) disclose interposer capacitors as techniques of reducing L. FIG. 15 shows the structure of an interposer capacitor disclosed in Patent Document 3.
In FIG. 15, a silicon substrate 100 includes a first through-hole 120a whose inside space is filled with a conductor. On a support member 110 composed of the substrate 100, a bottom electrode 140, a high dielectric film 160, and a top electrode 180 are laminated together to form a capacitor. The bottom electrode 140 of the capacitor is connected to an electrode pad 240a and a bump electrode 280a via the conductor of the through-hole 120a. The bump electrode 280a is connected to a power line of a circuit board. Additionally, the bottom electrode 140 is connected to a power line of an LSI chip via an electrode pad 210a. The top electrode 180 of the capacitor is connected to an electrode pad 240b and a bump electrode 280b via a conductor filled in the inside space of a through-hole 120b. The bump electrode 280b is connected to a ground line of the circuit board. Additionally, the top electrode 180 is connected to the ground line of the LSI chip via an electrode pad 210b. The electrode pads 210a, 210b, 240a, 240b are formed on protective films 200 and 220.
Capacitors with the μF order of high capacitance, which meet the GHz order of high-speed processing of LSI chips, need large areas equivalent to areas of LSI chips; however, a problem arises owing to difficulty in forming large-area capacitors using thin films. This is because large-area capacitors, equivalent to the size of an LSI chip, suffer from a problem in that short-circuits may occur due to defects of dielectric films when particles occur in deposition processes. To solve this problem, some documents (e.g. Patent Document 7) disclose specific techniques regarding capacitors whose dielectric layers are composed of anodic oxidation films easily facilitating large-area capacitors. However, another problem arises in the technique of Patent Document 7 in that capacitance of capacitors cannot be increased due to a small dielectric constant of an anodic oxidation film than a dielectric constant of an oxidation thin film having a perovskite structure.
As the method of detecting defects in wires and diffused layers of semiconductor devices, some documents (e.g. Patent Document 8) disclose a method of measuring resistance variation, wherein they refer to the actual utilization of OBIRCH (Optical Beam Induced Resistance Change) analysis. OBIRCH analysis has been used for defects analysis on semiconductor devices and finished products of capacitors, whereas it can be used to detect short-circuits between top electrodes and bottom electrodes of capacitors.